1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to three-dimensional memory (3D-M).
2. Prior Arts
Three-dimensional memory (3D-M) is a monolithic semiconductor memory comprising a plurality of vertically stacked memory cells. It includes three-dimensional read-only memory (3D-ROM) and three-dimensional random-access memory (3D-RAM). The 3D-ROM can be further categorized into three-dimensional mask-programmed read-only memory (3D-MPROM) and three-dimensional electrically-programmable read-only memory (3D-EPROM). A 3D-M's memory cell could be a memristor, a resistive random-access memory (RRAM or ReRAM), a phase-change memory, a programmable metallization cell (PMC), or a conductive-bridging random-access memory (CBRAM).
U.S. Pat. No. 5,835,396 issued to Zhang on Nov. 3, 1998 discloses a 3D-M, more particularly a 3D-ROM. As illustrated in FIG. 1A, a 3D-M die 20 comprises a substrate level 0K and a plurality of vertically stacked memory levels 16A, 16B. The substrate level 0K comprises transistors 0t and interconnects 0i. Transistors 0t are formed in a semiconductor substrate 0, while interconnects 0i, including substrate metal layers 0M1, 0M2, are formed above the substrate 0 but below the lowest memory level 16A.
The memory levels (e.g., 16A) are coupled to the substrate 0 through contact vias (e.g., 1av). Each of the memory levels (e.g., 16A) comprises a plurality of upper address lines (e.g., 2a), lower address lines (e.g., 1a) and memory cells (e.g., 5aa). Adjacent memory cells are coupled by the address lines, which are horizontal in this example. It is well known by those skilled in the art that adjacent memory cells in a 3D-M could be coupled by horizontal address lines, vertical address lines or a combination thereof. The memory cells could comprise diodes, transistors or other devices. Among all types of memory cells, the diode-based memory cells are of particular interest between they have the smallest size of ˜4F2, where F is the minimum feature size. Since they are generally formed at the cross points between the upper and lower address lines, the diode-based memory cells can form a cross-point array. Hereinafter, diode is broadly interpreted as any two-terminal device whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. In one exemplary embodiment, diode is a semiconductor diode, e.g., p-i-n silicon diode. In another exemplary embodiment, diode is a metal-oxide diode, e.g., titanium-oxide diode, nickel-oxide diode.
In this figure, the memory levels 16A, 16B form at least a 3D-M array 16, while the substrate level 0K comprises the peripheral circuits for the 3D-M array 16. A first portion of the peripheral circuits are located underneath the 3D-M array 16 and therefore, referred to as under-array peripheral circuit. A second portion of the peripheral circuits are located outside the 3D-M array 16 and therefore, referred to as outside-array peripheral circuits 18. Because the space 17 above the outside-array peripheral circuits 18 does not contain any memory cells, it is wasted.
U.S. Pat. No. 7,383,476 issued to Crowley et al. on Jun. 3, 2008 discloses an integrated 3D-M die 20. The integrated 3D-M die 20 comprises all necessary peripheral-circuit components for a standalone integrated 3D-M die 20 to perform basic memory functions, i.e., it can directly use the voltage supply 23 provided by a user (e.g. a host device), directly read data 27 from the user and directly write data 27 to the user.
As illustrated in FIG. 1B, the integrated 3D-M die 20 comprises a 3D-array region 22 and a peripheral-circuit region 28. The 3D-array region 22 comprises a plurality of 3D-M arrays (e.g., 22aa, 22ay) and their decoders (e.g., 24, 24G). These decoders include local decoders 24 and global decoders 24G. The local decoder 24 decodes address for a single 3D-M array, while the global decoder 24G decodes address to each 3D-M array.
The peripheral-circuit region 28 comprises read/write-voltage generator (VR/VW-generator) 21 and address/data translator (A/D-translator) 29. The VR/VW-generator 21 provides read voltage VR and/or write (programming) voltage VW to the 3D-M array(s). The A/D-translator 29 converts address and data from a logical space to a physical space and/or vice versa. Here, the logical space is the space viewed from the perspective of a user (e.g., a host device) of the 3D-M, while the physical space is the space viewed from the perspective of the 3D-M.
The VR/VW-generator 21 includes a band gap reference generator (precision reference generator) 21B, a VR generator 21R and a charge pump 21W. Among them, the VR generator 21R generates the read voltage VR, while the charge pump 21W generates the write voltage VW (referring to U.S. Pat. No. 6,486,728, “Multi-Stage Charge Pump”, issued to Kleveland on Nov. 26, 2002). The prior-art integrated 3D-M die 20 generates both read voltage and write voltage internally.
The A/D-translator 29 includes address translator and data translator. The address translator converts a logical address to a physical address and/or vice versa, while the data translator converts a logical data to a physical data and/or vice versa. Hereinafter, the logical address is the address at which data appears to reside from the perspective of the user and the physical address is the memory address that is represented on the address bus of the memory. Similarly, the logical data is the data transmitted from or received by the user and the physical data is the data that are physically stored in the memory cells. Note that the logical address/data are represented on the input/output 27 of the 3D-M die 20, while the physical address/data are represented on the internal bus 25 directly coupled to the 3D-M array(s) 22.
The A/D-translator 29 of FIG. 1B includes an error checking & correction (ECC) circuit 29E, a page register/fault memory 29P and a smart write controller 29W. The ECC circuit 29E detects and corrects errors while performing ECC-decoding after data are read out from the 3D-M array(s) (referring to U.S. Pat. No. 6,591,394, “Three-Dimensional Memory Array and Method for Storing Data Bits and ECC Bits Therein” issued to Lee et al. on Jul. 8, 2003). The page register/fault memory 29P serves as an intermediate storage device with respect to the user and the 3D-M array(s) (referring to U.S. Pat. No. 8,223,525, “Page Register Outside Array and Sense Amplifier Interface”, issued to Balakrishnan et al. on Jul. 17, 2012). It performs ECC-encoding before data are written to the 3D-M array(s). The smart write controller 29W collects detected errors during programming and activates the self-repair mechanism which will reprogram the data in a redundant row (referring to U.S. Pat. No. 7,219,271, “Memory Device and Method for Redundancy/Self-Repair”, issued to Kleveland et al. on May 15, 2007). The prior-art integrated 3D-M die 20 performs both address translation and data translation internally.
The VR/VW-generator 21 and A/D-translator 29 are outside-array peripheral-circuit components 18. Because they occupy a large area on the 3D-M die 20, the prior-art integrated 3D-M die 20 has a low array efficiency. The array efficiency is defined as the ratio between the total memory area (i.e., the chip area used for memory) and the total chip area. In 3D-M, the total memory area (AM) is the chip area directly underneath user-addressable bits (i.e., not counting bits a user cannot access) and can be expressed as AM=Ac*CL=(4F2)*C3D-M/N, where CL is the storage capacity per memory level, Ac is the area of a single memory cell, C3D-M is the total storage capacity of the 3D-M, F is the address-line pitch, and N is the total number of memory levels in the 3D-M. In the following paragraphs, two 3D-M dies are examined for their array efficiencies.
As a first example, a 3-D one-time-programmable memory (3D-OTP) is disclosed in Crowley et al. “512 Mb PROM with 8 Layers of Antifuse/Diode Cells” (referring to 2003 International Solid-State Circuits Conference, FIG. 16.4.5). This 3D-OTP die has a storage capacity of 512 Mb and comprises eight memory levels manufactured at 0.25 um node. The total memory area is 4*(0.25 um)2*512 Mb/8=16 mm2. With a total chip area of 48.3 mm2, the array efficiency of the 3D-OTP die is ˜33%.
As a second example, a 3-D resistive random-access memory (3D-ReRAM) is disclosed in Liu et al. “A 130.7 mm2 2-Layer 32 Gb ReRAM Memory Device in 24 nm Technology” (referring to 2013 International Solid-State Circuits Conference, FIG. 12.1.7). This 3D-ReRAM die has a storage capacity of 32 Gb and comprises two memory levels manufactured at 24 nm node. The total memory area is 4*(24 nm)2*32 Gb/2=36.8 mm2. With a total chip area of 130.7 mm2, the array efficiency of the 3D-ReRAM die is ˜28%.
In the prior-art integrated 3D-M, its 3D-M arrays are integrated with all of its peripheral-circuit components. The peripheral-circuit components of the 3D-M include VR/VW-generator and A/D-translator. The integrated 3D-M is thought to be advantageous based on the prevailing belief that integration will lower the overall cost of an integrated circuit. However, this belief is no longer true for 3D-M. Because the 3D-M arrays use a complex back-end process while their peripheral circuits use a relatively simple back-end process, integrating the 3D-M arrays with their peripheral-circuit components will force the peripheral-circuit components to use the expensive manufacturing process for the 3D-M arrays. As a result, integration does not lower the overall cost of the 3D-M, but actually increases it. To make things worse, because they can only use the same number of the substrate metal layers (as few as two) as the 3D-M arrays, the peripheral-circuit components are difficult to design and occupy a large chip area. Finally, because the 3D-M cells generally require high-temperature processing, the peripheral-circuit components need to use high-temperature interconnect materials, e.g., tungsten (W). This degrades the 3D-M performance.